Memory Cell FAIL

THIS DOESN'T WORK.   See that junction just above the DATA IN transistor?   Well there's a path through the 10k, LED and 330R to 3.3V, so that transistor is always powered and so when DATA IN goes high it sets the flip flop state, regardless of WRITE ENABLE.

I'm leaving this page as is - there's more to be learnt from failures than sucesses.



I'm aiming for six registers at 16 bits each and I'm expecting the transistors used to be the majority of the total transistor count, that means that the memory cell design is critical for determining the transistor count.   The transistor count is both important in terms of cost but also ease of construction, portability, etc.

It's an absolute requirement that the workings of the processor are visible, so that means driving an LED so that the state of every bit can be seen.   This rules out any capacitor driven DRAM (large capacitors are too expensive).    On 27Nov16 I got my first four transistor SRAM cell working and on 04Dec16 the second.


The central part is a standard flip-flop with white LEDs in the load path.   The left hand side is the write circuit, if writeEnable is low then nothing happens nothing flows to the flip-flop.   if writeEnable is high then dataIn sets the state of the flip-flop.   Similarly with readEnable, provided it is high then the state of the flip-flop is available on dataOut.   One runs at 450kHz, the other at 400kHz for many billions of random write/read cycles without error.

Interestingly, the LEDs speed up this circuit.    Maybe that's because there is a voltage drop across them, measured at white 2.8V, red 1.7V, green 2.5V, blue 2.65V.