Status

I have:
  • An architecture that seems to work well, simple yet complete and efficient
  • One bit of working memory (various designs)
  • One bit slice of the ALU including fast carry
  • A working emulator (which will be used as a run-time check)
  • An assembler
  • A Forth style language including basic operations, control flow, multiply and divide (16, 32 and 64 bit integers, floating point) and some OS calls.
  • Two RPi3s talking back to back at acceptable speed over GPIO, so I believe that a RPi can be used as clock, memory, IO and as a sanity check.
Which may not seem like a lot, but it's definitely coming together.

Current major tasks are:
  • Write in pyRTL and if possible implement on FPGA
  • Finalise the hardware design
    1. Finish the memory cell and test at reasonable scale
    2. Clarify the carry propagate (fix the bug one way or another)
    3. Minimise the ALU
    4. Design all the control logic
  • DIY PCB - the idea is to print onto A4 and paste onto card.  Drill holes through, poke many component legs through same hole and solder on reverse
  • Find the time to build it all
Current minor tasks are: 
  • Should the data stack be descending not ascending?  A descending stack would have little endian variables and would copy to memory better as it's natural to point to the start, not end, of a memory block.  The call stack can remain descending, it's small and the other end of the data stack can be the heap.
  • Profile the instructions actually used - most must never be used.   I'm pretty confident about the instruction set at this stage.
  • Understand fbcc and get it going - it's the only way I'll find out what I'm missing.
  • Look at tcc (or maybe lcc) - can I port it to my instruction set where everything is 16 bits?